Collection of IP-cores for FPGA & ASIC written on Verilog/VHDL #FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera PS: also might be intresting @fpgasic
Subscribers
1,213
Avg views
97
Engagement rate
8%
CPM (est.)
—
Creatives seen
—
Channel age: 2,702 days
Audience quality
Looks reliableView rate: 8%
- Reach and engagement sit in a normal range for this size
An estimate from public metrics — we have no admin access to Telegram’s native analytics, so treat this as a signal, not a verdict.
Building history
We have not collected enough daily snapshots yet to plot a trend. The current snapshot is shown above; a chart will appear once we have at least two data points.
Explore
Last refreshed: 2026-07-16